1. Technical Field
This disclosure relates generally to processors, and, more specifically, to direct memory access and programmed input/output operations in processors.
2. Description of the Related Art
In various computer architectures, a programmed input/output (PIO) operation may be used by a processor to access a target device, such as keyboards, mice, network cards, flash controllers, etc. The access may include transmitting or receiving data to or from the target device, or setting up direct memory access (DMA) operations on the target device, which allow direct access between memory and a target device independent of the processor.
In certain environments, PIO and DMA operations share a common path to target devices. As a result, several sources of latency may exist in performing PIO operations and corresponding DMA operations. First, when performing a multi-beat, multi-clock cycle DMA burst, a subsequent PIO operation (e.g., to set up a future DMA operation) may need to wait for all beats of the DMA burst to complete before performing the PIO operation. Thus, the subsequent PIO operation is delayed, as is any future corresponding DMA operation. Second, setting up a future DMA operation may require multiple clock cycles to complete a PIO operation, or may require multiple PIO operations. Thus, in some scenarios, each cycle of a PIO operation, or each PIO operation, must potentially wait for other DMA bursts to complete further compounding the delay for the full PIO operation to complete. Over the course of several PIO setup/DMA operation sequences, delays may aggregate and significantly impact the system. The delay can be especially problematic when large amounts of data (e.g., videos or images) need to be transferred using DMA.